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• UG1001 – GateMate™FPGAPrim itives Library D ate Rem arks August 2021 Added DDR input to CC_ODDR prim tive in Section 1. starlight princes slot 10 on page 33. slot deposit pakai sakuku Added CC_PLL_ADVprim itive in Section 6 3 July 2021 Updated list of dedicated clock pins in Table 6 3 on page 77 Port RECFGadded to CC_CFG_CTRLprim itive in Section 6 4 from page 81 June 2021 Initial